The Background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly or impliedly admitted as prior art against the present disclosure.
Network devices, such as routers, switches, gateways, access points (AP), bridges, and concentrators, etc., may receive and retransmit wireline or wireless data, which may be in the form of packets. The network devices may also examine packets to determine appropriate packet destination addresses and may temporarily store the data for this purpose.
Packets include one or more header fields and a data field. Header fields may identify the packet source or destination, identify the protocol to be used to interpret the packet, and/or identify the packet position in a sequence of packets. The data field may contain any type of digital data.
Referring to FIG. 1, network devices may use external memories, such as dynamic random access memories (DRAM) to store packets. To improve external memory/network device interface, reduced latency dynamic random access memories (RL-DRAM) have been developed.
To optimize performance of memory chip design, memory cell arrays on DRAM-type chips are arranged in banks. AN RL-DRAM 10 generally includes N banks 12-1, 12-2, . . . , and 12-N, where N may be set equal to 8. The multiple banks architecture allows higher memory utilization by parallelization.
Referring now to FIGS. 2 and 3, an RL-DRAM device has a row cycle time (TRC) limitation, i.e. the minimal access-to-access time. By having a multiple banks architecture, utilization can be optimized by parallel usage of all banks. FIG. 2 illustrates parallel access for a single bank (Bank 0), which allows access every TRC. FIG. 3, illustrates parallel access for multiple banks, Bank 0, Bank1, . . . , and Bank N, which allow N accesses in a TRC duration.
Referring now to FIGS. 1 and 4, a memory control module 16 of the network module 8 may send a packet to the RL-DRAM 10. Because packets may vary widely in length, a typical data packet 14 may be divided by a packet processor module 18 into a segmented packet 20 of M sections 20-1, 20-2, . . . , and 20-M or predefined bursts.
Referring again to FIG. 1, data is moved in and out of the RL-DRAM 10 by writing data to the N banks 12-1, 12-2, . . . , and 12-N in a “round-robin” fashion. In other words, a section of a packet is stored in the first bank 12-1 (Bank 0) and another section is stored in the second bank 12-2 (Bank 1). The section bank allocation is moved from bank to bank as illustrated by arrow 13 until it is stored in the Nth bank 12-N (Bank N−1). Therefore, when a continuous burst of small packets (which occupy a single section) should be stored to the RL-DRAM, the RL-DRAM is continuously accessed with the same bank number, i.e. Bank 0, at the beginning of the bank. Writing operations such as the “round-robin” fashion, that alternate communication between two or more memory banks, may be referred to as interleaving. This interleaving allows optimized utilization of the memory, since other banks are used during the latency delay of an accessed bank.